A technique has been put to practical use in which, in an information processing apparatus such as a server that performs various information processing, multiple power supply circuits such as AC-DC conversion circuits are disposed as power supply units, and information processing is performed by using electric power supplied from the multiple power supply circuits. By using multiple power supply circuits, even when a failure or performance degradation occurs in one power supply circuit and the amount of power supply decreases, the information processing apparatus is able to continue processing with power supplied from another or other power supply circuits.
However, in a case where a decrease in the amount of power supply occurs in one or some of the multiple power supply circuits, the load on another or other power supply circuits increases, which may cause a failure or the like to occur also in another or other power supply circuits. Throttling exits as a technique for addressing this problem. According to the throttling technique, in a case where the amount of power supply from one or some power supply circuits decreases in an information processing apparatus having multiple power supply circuits, the operating frequency of the processor of the information processing apparatus is decreased. By decreasing the operating frequency of the processor, power consumed by the processor is minimized to thereby reduce the load on another or other power supply circuits.
Like multi-node servers, information processing apparatuses having multiple arithmetic processing units have been put to practical use. Multi-node servers have the following advantage. That is, in a case where maintenance such as inspection or replacement is to be performed for one of the multiple arithmetic processing units, maintenance may be performed individually only on that specific arithmetic processing unit. It is possible for the multiple arithmetic processing units included in multi-node servers to both perform information processing individually and perform predetermined information processing in corporation with each other. Further, there are also cases where an information processing apparatus having multiple arithmetic processing units and another information processing apparatus are coupled via a network to thereby configure a single computer system, for example, a high performance computer (HPC) as a whole. In such cases, the multiple information processing apparatuses perform information processing in corporation with each other.
As related art, Japanese Laid-open Patent Publication No. 2012-051300 exists.